1. Field of the Invention
The present invention relates to an interface for a semiconductor device, and more particularly to an interface circuit and an interfacing method suitable for a high-speed semiconductor device.
2. Discussion of Related Art
As the operational speed of semiconductor chips increase, the need for a low power supply voltage and high-speed interface-circuits also increase. A lower supply voltage decreases power dissipation and reduces transmission line effects in high-speed operations. There has been a trend towards decreasing the power supply voltage applied to high speed semiconductor chips, for example, from 5 volts (V) to 3.3V, 2.5V, or less than 2.5V. For example, for a highly integrated semiconductor device having a gate poly size of less than 0.18 xcexcm, and employing a dual oxide manufacture process to form a thin tunnel oxide, the internal power supply voltage is about 1.8V. Integrated circuit chips typically include an internal voltage controller for dropping the external power supply voltage applied from an exterior to the internal voltage needed for internal circuits. For example, a random access memory (RAM) is described with a voltage reduction circuit mounted as an internal voltage controller for reducing the voltage applied to an internal circuit in Japanese Patent Publication No. 9-270191. 
An input receiver can be used as an interface circuit for buffering an external signal to a level appropriate for the internal circuits of a semiconductor chip. As its name implies, an interface circuit operates between the internals of an integrated circuit and any external components. The voltage levels output, and setup and hold times are important parameters of an input receiver.
Typically, the input receiver is designed to have a signal interface such as a LVTTL, HSTL, or GTL, according to the needs of the particular semiconductor device. The LVTTL interface is commonly used in current designs.
For example, an LVTTL interface wherein the external power supply voltage (hereinafter, EXTVDD) is 3.3V (or 2.5V), while the internal power supply voltage is 1.8V or some voltage less than EXTVDD. The reduced internal voltage provides a decrease in transition time with increased speed and a decreased operation current.
However, in the case of an internal power supply voltage less than EXTVDD-1Vt (Vt is a threshold voltage), the rising/falling time of an input signal is about 1v/1n, and a high level of the input signal is higher than the internal power supply voltage+1Vt, there is a problem in that the setup and hold time cannot be satisfied with accuracy. That is, when the level of the internal power supply voltage is about 1.8V, with a swing between Vil=0V and Vih=3V, and the rising/falling time of the input signal is about 1v/1n, the input receiver operates only when the level of the input signal is less than the internal power supply voltage-1vt at a transition from the high level to the low level. Accordingly, the rising/falling time of 1v/1n and the voltage swing at the LVTTL interface makes satisfaction of the setup/hold time tSU/tHD and optimization of a current consumption difficult.
Conventional input receivers are explained with reference to FIGS. 1 to 3. FIG. 1 shows an input receiver which includes p type and n type channel metal-oxide semiconductor (MOS) transistors PM1, PM2, NM1, NM2, a p-type channel MOS transistor PM3 and an inverter chain 20. The inverter type input receiver receives an input signal XAi through gates of the p type and n type channel MOS transistors PM2, NM1. A control signal ZZB applied to the gate of NM2 puts the receiver in a waiting current mode. When the control signal ZZB is applied at a level turning on the MOS transistor NM2 and the input signal XAi is applied at a low level. Node NO1 is pulled up to EXTVDD at a logic xe2x80x9chighxe2x80x9d, which is applied to inverter I1 of the inverter chain 20. An internal power supply voltage IVC is applied to the inverter chain 20. Although the inverse output signal is buffered to the level of the internal power supply voltage by the inverter chain 20 and a delay of the output signal OUT is adjusted to suit a phase of a clock signal, the delay is difficult to adjust accurately for each transition. For example, when a rising/falling time of the input signal (hereinafter RFF) is 1v/1n and the input signal swings between OV and 3V (here, the external power supply voltage is 3.3V and the internal power supply voltage is 1.8V), H-L time (or L-H time) becomes xe2x80x9c1.5ns(EXTVDD-IVC)+PMOS Vt/RFTxe2x80x9d in order to turn on PMOS at the first stage of the inverter (or the second stage), and therefore application of this receiver in a high-speed semiconductor device is not suitable. Accordingly, as shown in FIG. 1, when the input signal XAi is changed from low level to high level (or vise versa), it is difficult to adjust each delay. In addition, when the internal power supply voltage is less than EXTVDDxe2x80x941Vt and a rising/falling time of an input signal is large and a high level of the input signal is more than the internal power supply voltage+1Vt, the above described input receiver cannot meet the setup/hold time tSU/tHD requirements.
With respect to FIG. 2, an amplifier type input receiver is shown for sensing voltage, including an inverter chain 20 and a current mirror type differential amplifier including P type and N type channel MOS transistors PM10, PM11, NM10, NM11, NM12, and NM13. In the input receiver shown in FIG. 2, an input signal XAi is input to a gate of n type channel MOS transistor NM10 as the first input signal, and a reference signal REFi is input to a gate of n type channel MOS transistor NM11 as the second input signal. The reference signal REFi and a control signal ZZB are applied to the gates of the n type channel MOS transistors NM12, NMI3, respectively. The current mirror type differential amplifier CDA functions as a voltage sense amplifier for sensing voltage. Here, the reference signal REFi is a reference voltage signal formed in a semiconductor device. As in FIG. 1, the input receiver structure of FIG. 2 also has a problem when the internal power supply voltage is less than EXTVDDxe2x80x941Vt, a rising/falling time of an input signal is large, and a high level of the input signal is more than the internal power supply voltage+1Vt. That is, where an output signal at an output node NO11 of the sense amplifier is applied to the delay chain 20 to be changed to a level of the internal power supply voltage. A driving capability of a driver transistor constituting the delay chain can be variable when the output signal of the sense amplifier CDA is changed from the high level to the low level.
With respect to FIG. 3, similarly to FIG. 2, an input receiver is shown which includes an inverter chain 20 and a current mirror type differential amplifier CDA including an inverter 110 and p type and n type channel MOS transistors PM10, PM11, NM10, NM11, NM13. The input receiver shown in FIG. 3 receives an input signal XAi through a gate of the n type channel MOS transistor NM10 as the first input signal, and receives an inverted signal of the input signal XAi through a gate of the n type channel MOS transistor NM11 as the second input signal. To a gate of the n type channel MOS transistor NM13 acting as a current source is applied a control signal ZZB. This current mirror type differential amplifier CDA functions as a voltage sense amplifier for sensing voltage. The input receiver of FIG. 3 has a driving power supply for the differential amplifier CDA and an inverter inverting the first input signal Xai. The input receiver is powered by the external power supply voltage EXTVDD, and a driving power supply of the delay chain 20 receiving an output signal at the output node NO11 of the sense amplifier is powered by the internal power supply voltage, whereby this also has the same problem as mentioned with respect to FIGS. 1 and 2.
Accordingly, a need exists for an input receiver which is capable of meeting setup/hold time requirements, having a low consumption of DC current even when the internal power supply voltage is less than EXTVDD minus a threshold voltage, a rising/falling time of an input signal is large, and a high level of the input signal is more than the internal power supply voltage plus a threshold voltage.
An object of the present invention is to provide a high-speed interface circuit suitable for a high-speed semiconductor device.
Another object of the invention is to provide an input receiver which keeps a tight setup/hold time with a low consumption of DC current even when the internal power supply voltage is less than the external power supply voltage minus a threshold voltage, a rising/falling time of an input signal is large, and a high level of the input signal is more than the internal power supply voltage plus a threshold voltage.
Still another object of the invention is to provide an input circuit having a good interface capability and low leakage of current while increasing (or maximizing) a transition speed and a method thereof.
According to one embodiment of the present invention, an interface circuit is provided for a semiconductor device, wherein the interface circuit includes an input driver producing a first and second output signal having opposite phases to each other by receiving an external power supply voltage as an operation voltage and buffering an input signal to the level of the external power supply voltage. The interface circuit also includes a cross-coupled sense amplifier for receiving an internal power supply voltage as an operation voltage when a control signal is in the first transition state, and performing a differential amplification by receiving the first output signal at a first input end and receiving the second output signal at a second input end. An output potential fixation element is also provided as part of the interface circuit for keeping a potential of an output end of the cross-coupled sense amplifier at a uniform potential corresponding to a level of the internal power supply voltage only when the control signal is in the second transition state. The interface circuit also includes an output driver for receiving the internal power supply voltage as an operation voltage and buffering the output signal at the output end into the level of the internal power supply voltage to be applied into a circuit in the chip.
In addition, according to another embodiment of the present invention, a semiconductor device uses a first power supply voltage and a second power supply voltage less than the first power supply voltage minus a threshold voltage, a method for interfacing an input signal to swing to a level of the first power supply voltage includes; a step of producing the first, the second output signal having opposite phases to each other by buffering the input signal with a use of the first power supply voltage as a driving power supply; a step of performing a level shifting through an cross-coupled type differential amplifier by using the second power supply voltage as a driving power supply and receiving the first output signal at a first input end and receiving the second output signal at a second input end; a step for finally outputting an output signal by buffering the level-shifted output signal to the level of the second power supply voltage with a use of the second power supply voltage as a driving power supply.
According to the invention explained above, advantages of the present invention include a high-speed response feature, the satisfaction of a setup/hold time requirement, and reduced DC current consumption when the internal power supply voltage is less than the external power supple voltage minus a threshold voltage and a rising/falling time of an input signal is large and a high level of the input signal is more than the internal power supply voltage plus a threshold voltage.
Above mentioned objects and other objects, features and advantages of the invention will be more clear in a detail description for preferable embodiments of the invention which is explained hereinafter in regard to appended drawings. It should be noted that the same or similar parts in figures are represented with the same or similar reference marks for the convenience""s sake for an explanation and understanding.